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Sayma v2 meeting number 6

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Joe Britton edited this page Feb 22, 2019 · 1 revision
  • Location: Google hangout
  • Date and time: 2019-02-18 14:00 UTC, start 14:05
  • Chair: TH
  • Minutes: RJ
  • Participants:
    • AK, Anna Kaminska
    • PK, Paweł Kulik
    • RJ, Robert Jördens
    • MS, Mikolaj Sowiński
    • TH, Tom Harty
    • JB, Joe Britton
    • SB, Sébastien Bourdeauducq (ABSENT)
    • GK, Greg Kasprowicz (ABSENT)

Agenda from TH

  1. Accept previous minutes: https://github.com/sinara-hw/sinara/wiki/Minutes20190129-Sayma-v2
  2. Progress on power supply issues
  3. Can we make a decision about SYSREF generation (HMC7043/delay line)? If not, agree on what other tests need to be done before decision making, who will perform them and what's the time frame?
  4. SB, can you summarise your findings with DDMTD on Ultrascale and comment on their implications for WR (both for Sayma used in a rack with Metlino and for use as a standalone slave with Kasli DRTIO via SFP)
  5. Status of M-Labs stub port of ARTIQ for Sayma v2.0
  6. Agree on final time line for Sayma v2.0 going to manufacture
  7. Discuss SB's suggestion for adding a "timing FPGA to Metlino".
  8. Discuss Metlino FPGA. Can we avoid Ultrascale? Or, too late in the design process? Assuming ARTIQ Zynq ports go ahead, in the long run we may wish to switch metlino to a Zynq FPGA anyway, so there is room to rethink things when we do that.
  9. AOB

1. Accept previous minutes

2. Power supply

Progress on power supply issues

  • TH is still nervous
  • PK: Creotech hasn't seen the 3.3 V problems on their Sayma v1
  • consensus: Decision lies in hands of Creotech to decide if recently conducted tests on AFCZ are adequate and resolve whether Exar chips will work correctly for Sayma v2.
  • GK did the AFCZ tests but is absent. So discussion was inadequate.
  • GK responded by email later
I will publish simulation sources and results so it would take a moment for Xilinx team to review it.

I finally found what was a problem with DC drop. It was not really caused by the wrong simulation but by the fact that the PCB workshop increased clearances around the vias which caused DRC increase of the supply plane. Another issue was missing compensation resistor.

3. HMC7043/delay line

Can we make a decision about SYSREF generation (HMC7043/delay line)? If not, agree on what other tests need to be done before decision making, who will perform them and what's the time frame?

  • TH no longer concerned with small glitches or thermal drift. Recalls that SB still sees large glitches.

  • SB responded by email shortly after pointing to his email on 2/11.

Synchronization with HMC7043 vs. discrete elements.

Advantages of the discrete elements:
* conceptually simpler.
* removes high-precision timing from FPGAs that are potentially noisy 
and with significant voltage/temperature effects.
* nodes can be inspected with a fast scope for debugging.

Advantages of the HMC7043:
* testable on the current boards; development can continue while v2 
boards are being made, and v1 boards can serve as a reference to debug 
v2 boards.
* very good skew/jitter performance (e.g. I've seen that path to the DAC 
is fully deterministic to 1 step of the 25ps analog delay); the discrete 
element circuit is more risky there.
* dividers can (in theory) be slipped, so there is no need for PLL 
brute-force techniques at low frequencies.
* once configured, generates a SYSREF signal going *into* the FPGA, 
which is a somewhat more conventional way of using JESD204.

If we have to make the decision now, I'd say keep the HMC7043. I'd 
prefer to see a reproduction of my results and what the signals look 
like on a fast scope, but I cannot attribute current synchronization 
bugs to HMC7043-specific problems.

  • TH is working on conducting tests requested by SB. It's taking a while because he's in the process of making test setup less flaky by moving the boards into a rack, and integrating Sayma with our buildbot/CI.

  • TH received 2 Sayma AMC + RTM v1.0 from UMD to support testing.

  • JB supports choice to use HMC7043. Nobody present objects. Proceed with HMC7043.

  • PK will reopen v2 issues related HMC7043

4. DDMTD on Ultrascale

SB, can you summarise your findings with DDMTD on Ultrascale and comment on their implications for WR (both for Sayma used in a rack with Metlino and for use as a standalone slave with Kasli DRTIO via SFP)

  • SB was not present. Informed discussion needs SB input but conversation continued anyway.
  • By email SB had raised concern about use of UltraScale FPGAs
  • TH: When Oxford tested DDMTD on UltraScale he assumed that the transceivers could be deterministically reset. But SB has seen things that indicate otherwise. This relates to ongoing discussion about putting timing FPGA on Metlino
  • TH: points out it's unclear how to proceed at this point. Another round of tests is needed using Sayma v1.
  • TH: proposes to keep focus on Sayma v2 today

5. Stub Port

Status of M-Labs stub port of ARTIQ for Sayma v2.0

  • RJ: M-Labs hasn't started work on this. Says SB wants more funding.
  • JB: SB hasn't asked for more funding.
  • RJ: They have net list from FPGAs from GK.
  • TH: observes that resolving M-Labs funding seems to be a big road block
  • TH: Suggests building more flexibility into contract for Software and Gateware Developer
  • Discuss further offline.

6. Sayma v2 sign off timeline

Agree on final time line for Sayma v2.0 going to manufacture

  • all: Consensus is that we agree on freezing the design features. HMC7043 was the last uncertainty, now resolved.
  • RJ: M-Labs can't sign off on v2.0 design until stub port is complete.
  • PK: Creotech has a copy of Ultium Designer.
  • AK: We need a final design. JB approved list of long lead time parts last week. But we need to know set of all components.
  • TH: Need updated drawings in Ultium Designer format ... Need this resolved by Greg
  • GK was absent
  • TH: Oxford continues to setup to test Sayma in house

RCAP: Tasks remaining prior to final sign-off on Sayma v2 schematics.

  1. SB: stub port
  2. TH: confirmation that HMC7043 code supplied by SB produces reproducible results
  3. GK: Ultium Designer schematics and layout
  4. Creotech: sign-off on Ultium schematics and layout

7. Timing FPGA for Metlino

Discuss SB's suggestion for adding a "timing FPGA to Metlino".

SB was not present so there was not an informed discussion.

8. Discuss Metlino FPGA

Can we avoid Ultrascale? Or, too late in the design process? Assuming ARTIQ Zynq ports go ahead, in the long run we may wish to switch metlino to a Zynq FPGA anyway, so there is room to rethink things when we do that.

  • TH: proposed to keep discussion about Sayma for now.

9. Conclusion

  • Next meeting: 2019-03-04 14:00 UTC

    • MC: JB
    • Minutes: TH

  • Discussion of how the present meeting went.

    • missing was SB and Greg
    • agenda wasn't sent early enough
    • wasn't clear that the meeting would actually happen
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