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Minutes20190318 Sayma v2
MC: Greg, Notes: Joe
Present: Greg, Joe, Tom (arrived late), Robert, Sebastien (missed most of meeting due to communication problems), Paweł, Anna, Mikołaj (missed first 10 minutes due to communication problems)
- Creotech contract grant date
- Accept previous minutes: https://github.com/sinara-hw/sinara/wiki/Minutes20190311-Sayma-v2
- Status of Sayma AMC and RTM review.
- Status of Sayma AMC and RTM stub ports
- Schedule next meeting, MC and minutes
- Review meeting quality
Deadline for Creotech grant that funds labor on Sayma v2 expires May 1. JWB asks what work can Creotech do prior to May 1 in the absence of fully stuffed Sayma v2 hardware.
- Pawel: Some coding could be done in advance. But better to do with real hardware on hand. Duplication of effort is unpleasant.
- Greg: Documentation and schematics could be done in advance. For example clock schematics, SPI trees, transceiver routing.
- Joe: Suggests building acceptance tests in advance HT3 .
- Mikołaj: "a lot" is already done for AMC, needs testing
- Joe: What is "a lot"?
- Anna: Let's continue discussion by email
No objections to previous minutes: https://github.com/sinara-hw/sinara/wiki/Minutes20190311-Sayma-v2
What is status of Sayma AMC and RTM stub ports?
- Joe: AMC stub port is done. Is M-Labs ready to sign off on parts of AMC review they conducted?
- Robert: Sebastien handled this; ask him
- Joe: is RTM stub port finished?
- RJ: RTM stub port is started but not finished
- Joe: Is there anything pending for stub port of RTM to be finished?
- RJ: Have to ask Sebastien
- NOTE: Sebastien had connectivity problems and could listen but not respond
SB sent email in followup.
Sayma AMC:
- Checked clock topology (written up brief summary of clock signals and their expected uses). Checked that signal names reflect their functions
- grounding of clock coax connectors
- AMC<->RTM signal connectivity. Particularly, number of LVDS lines required for RTM AFE mezzanines (and ensured that we have sufficient CC pins for LVDS ADCs)
- checked WR implementation (both with external DFF and using FPGA DFFs): choice of helper + main DCXOs; signal connectivity; access to recovered clock from FPGA; distribution of CDR clocks; ability to switch between SI5324 and WR; all WR signals go to same FPGA bank
- test points and debug connectors Sayma RTM:
- AMC <-> RTM connectivity (clocks between the two boards; LVDS lines; CC pins)
- HMC830: power cycler; passive and active loop filters; routing of input (reference) and output clock; supplies
- test points and debug connectors
- wr/clock recovery (as on AMC but without external DFF)
- HMC7043 connectivity; disabling RF outputs until after chip configured
- AFE mezzanine connectivity (reference clocks; LVDS lines and CC pins; RTM LVCMOS IO; I2C; power supplies)
Other than the SDRAM (https://github.com/sinara-hw/Sayma_AMC/issues/71) and the transceiver clocking option from the RTM (https://github.com/sinara-hw/Sayma_AMC/issues/72) the AMC generally looks good, so let's move forward with the Creotech reviews and the prototypes.
With the RTM so far my only major issue is this clocking "detail": https://github.com/sinara-hw/Sayma_RTM/issues/68
- Joe: What is status of review? When do we start routing?
- Tom: finished his AMC and RTM review on the weekend
- Robert: M-Labs review of AMC is the stub port
- Pawel: Tom and M-Labs, please give list of what was checked
- Tom: Looked into lots of things, hard to put into a concise list.
- Robert: finished his AMC/RTM review
- Tom: says he has signed off on AMC.
- Joe: How long for Creotech to do review?
- Pawel: won't have time until the end of the week
- Joe: How long for Greg to do layout and simulation?
- Greg: Could be done by end of this month. Another month to print and stuff.
TH sent followup email on 3/22.
Reviewed AMC FPGA pin assignments, including I/O voltages, on Sayma AMC 2.0rc5 around 64-bit SDRAM, 32-bit SDRAM (found issue), WR DDMTD, SFPs, SPI flash, RTM FPGA configuration(), RGMII Ethernet, SMA TTLs, serwb(), "GT16" DRTIO to RTM(), Si5324, DAC JESD204(), FMC connector, USB UART.
(*) Someone should still double-check that the AMC-RTM connector pin mapping is sensible and matches the platform file in Migen (e.g. HMC7043 output to the right AMC FPGA pin etc.) when the AMC and RTM are put together.
- [OK] Si5324 outputs aren't synchronized - use external clock buffer to feed GT clock, fabric clock and uFL
- [OK] Drive WR PLL with dedicated transceiver pins and OBUFDS_GTE3. Option to drive from fabric via capacitor selection for purposes of testing and working around any transceiver issues.
- [OK] Ethernet must have XO on transceiver pins.
- [OK] WR PLL output to fabric, GT and SMA
- [OK] check that CLOCK_DEDICATED_ROUTE is no longer necessary for siphaser
- [OK] make sure all transceiver channels can be clocked from uFL
- the issues I reported: https://github.com/sinara-hw/Sayma_AMC/issues?utf8=%E2%9C%93&q=is%3Aissue+author%3Asbourdeauducq+
With apologies for the delay, a list of things I looked at is below. NB I also checked quite a few misc things like max voltage rating, compatibility of logic standards, etc. However, I think Creotech should re-check all of those things in a more systematic way so I haven't explicitly listed them here. I've raised issues on GitHub for everything I spotted in my review. Once those are closed I'm happy to sign off on the schematics!
- Next meeting: 2019-03-25, 14:00, MC: Mikołaj, Minutes: Greg
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