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Minutes20190325 Sayma v2

Greg Kasprowicz edited this page Mar 25, 2019 · 3 revisions

MC: Mikolaj, Notes: Greg
Present: Greg, Joe, Tom , Robert, Sebastien , Paweł, Anna, Mikołaj

Agenda

  1. Accept previous minutes: https://github.com/sinara-hw/sinara/wiki/Minutes20190318-Sayma-v2
  2. Schematics verification:
  • FPGA connectivity verification
  • Do we want to check if closed issues are truly resolved?
  1. PCB layout verification:
  • Is Creotech the only responsible for all layout verification? Does anyone want to contribute this process?
  • Schedule on PCB layout verification.
  1. Status of Melino?
  2. Status of BaseMod?
  3. Schedule next meeting, MC and minutes
  4. Review meeting quality

1 Previous Minutes

No objections to previous minutes: 
https://github.com/sinara-hw/sinara/wiki/Minutes20190311-Sayma-v2

Robert: minor correction - I finished checks on Sayma AMC

2 Schematics verification

Mikolaj: FPGA connection verification - primarily done by Mlabs. One FPGA bank was mirrored on schematics, the question is if Mlabs verified schematics

Robert: we did stub port only

Pawel: the point is that FPGA connectivity still needs to be checked, stub port did not check i.e. if ref voltage was connected

Sebastien: in stub port, you don't tell where vref is connected

Greg: the problem would be found during layout but there were a lot of signals newly added and new issues can appear

Pawel: could Mlabs review other pins connected in right way? Other types of connections that cannot be checked with vivado, i.e. banks powered from right power sources

Greg: I found on RTM that bank was connected to wrong voltage by pure coincidence

Pawel: Mlabs could every connection to FPGA is in the way you wanted not only IOs. We will review other parts of the boards. We might have a problem with finishing it on time

Sebastien: does it affect Artiq?

Pawel: such mirrored bank would affect our test bench. And DCI termination.

Greg: the transition from CAD tool to CAD tool is problematic if we do changes in the meantime so cannot use double sync to avoid them

Robert: deadline?

Pawel: want to finish AMC sch review by Friday

Sebastien: a review including CTI work?

Pawel: Yes

Robert: we said 2 pairs of eyes, do this include FPGA?

Pawel: we checked already with previous revision so yes

Robert: we will review just the schematic of FPGA connectivity

Sebastien: does it include the netlist? The pin assignment in Excel sheet

Greg: nets were verified with stub port

Robert: yes, but does not take into account bank voltages

Sebastien: it would complain about diff voltage standards applied to same bank only

Robert: yes but does not care about voltage levels connected to FPGA Please just specify a list of priorities

Pawel: basically what I said, FPGA pinouts different than IOs, logic levels of driving sources, banks power rails

Mikolaj: we assume you will finish by Friday

Mikolaj: Should we check that issues were resolved ?

Greg: many are outtdated

Pawel: So we consider them resolved

Greg: Tom was looking at the issies I closed

3 PCB layout verification

Mikolaj: does any want to part in verification? CTI is the only responsible? We do all and you trust us ?

Greg: we will do it internally, the tools we use will do the job

Pawel: we wil ldiscuss the scope

Robert: don't have a time and cannot run on my machines

Pawel: it was just request if you can do.

Tom: will look at critical signals, scrreening, fitering, filters, PLL

Greg: A lot of changes, PHY moved closer to FPGA, clocks moved to quiter zone

Mikolaj: CTI is responsible for all layout verification Schedul before Easter, after it is long weekend with a lot of national holidays. We have to send PCBs to printing untill 17th of April or between 23-26 otherwise we won't be able to start manuf in April.

4. Status of Melino

Greg: Not practical to run Metlino production in same batch with Sayma. Providing that there are not too many changes to Metlino we can finish it until the April, 17th

Pawel: Make sure all the issues romm Sayma are fixed

5. Status of BaseMod

Pawel: checked schematics

Greg: PCB is not finished

Tom: I revieewed early version of schematics

Greg: Will create the relase and ask for review

Mikolaj: Not enough time to do a review for us, before end of April

Tom: the only i need when you will be finished, what is the timeline

Pawel: one week for review, AMC - till Friday, one week for pcb, in the mentime start schematic review of RTM- 2nd week of April, 3rd week of April review of RTM PCB and sch of Metlino,

Greg: all boards before end of April?

Pawel - all before 17 of April needs to be reviewed. Greg - the mest exp Saymas Je- concentrate on saymas only Greg - spending half of my time Rob - we cannot really put all on hold Ana - with other prijects ifts difficult, in april we have to prepare final report of grant. Joe - find a way to help Greg

6. Schedule next meeting

next meeting in a week time Rob - minutes, Tom, MOS

7. Meeting quality

Joe - great.

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