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Hard core CPUs
LiteX currently has minimal support (compiling and running BIOS, with UART serial terminal, connected to CSR bus in gateware) on these following hard ARM CPUs: Xilinx Zynq-7000, Xilinx UltraScale+ MPSoC, QuickLogic EOS S3, Gowin EMCU.
Note: producing working gateware on all these except Gowin EMCU currently requires patching LiteX locally in some way to remove address decoding on the CSR bus.
Demonstrated on Digilent Zedboard. As any complete workflow on Zynq devices requires a number of tools, scripts and build steps besides software and gateware binaries built by LiteX to produce and program boot images - refer to this repository for a complete implementation and details. Serial terminal is on the USB-UART.
Demonstrated on Xilinx KV260. Refer to the readme in this repository for a workflow allowing execution via JTAG. Serial terminal is on the USB-UART.
Demonstrated on QuickLogic QuickFeather.
Use python lib/litex-boards/litex_boards/targets/quicklogic_quickfeather.py --build
with path to QORC SDK provided in QORC_SDK environment variable to implement - refer to this repository for an example.
Serial terminal is on pins J3.2/J3.3.
Note: producing a working gateware currently requires patching LiteX locally in some way to remove address decoding on the CSR bus.
Demonstrated on Sipeed Tang Nano 4K.
To implement use python litex-boards/litex_boards/targets/sipeed_tang_nano_4k.py --cpu-type=gowin_emcu --build
. Program with Gowin Programmer in MCU mode using project.fs and bios.bin. Look at the platform file for the locations of the serial terminal pins.
Have a question or want to get in touch? Our IRC channel is #litex at irc.libera.chat.
- Welcome to LiteX
- LiteX's internals
- How to
- Create a minimal SoC-TODO
- Add a new Board-TODO
- Add a new Core-WIP
- Add a new CPU-WIP
- Reuse-a-(System)Verilog,-VHDL,-Amaranth,-Spinal-HDL,-Chisel-core
- Use LiteX on the Acorn CLE 215+
- Load application code the CPU(s)
- Use Host Bridges to control/debug a SoC
- Use LiteScope to debug a SoC
- JTAG/GDB Debugging with VexRiscv CPU
- JTAG/GDB Debugging with VexRiscv-SMP, NaxRiscv and VexiiRiscv CPUs
- Document a SoC
- How to (Advanced)