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Tutorials Resources
Lessons/Labs given to students to discover FPGAs and learn Migen/LiteX through a hands-on approach. These tutorials are covering the Migen's basics (syntax/simulations) through common SoC cores: Clock generation, 7-Segments displays, etc... and then the LiteX's basics through the integration of these cores in a SoC. It demonstrates and explains how to control these cores from an Host PC through a bridge (UART) and then directly from a RISC-V Soft-CPU implemented in the FPGA.
These tutorials should help users understand the possibilities of Migen/LiteX and give the basics to create their own Migen cores/LiteX SoCs.
Note: The labs are based on the Nexys4DDR (now named NexysA7) but can be easily adapted to others boards. Since these tutorials have been written, new less expensive open-source FPGA boards, also compatible with open-source FPGA toolchains, are widely available. The tutorials will probably be adapted to support such boards in the future.
A series of tutorials by fjullien focused on teaching Migen and LiteX. These hands-on labs help users understand FPGA design, SoC integration, and the creation of custom cores using Migen, alongside building complete systems with LiteX.
The Fomu is a tiny FPGA board that fits in your USB port. The SoC of the FPGA is built with LiteX and the workshop provides a hands-on approach to control the peripherals from a Host PC through the USB bridge from the ValentyUSB core and then demonstrates how to create a RISC-V SoC with a VexRiscv CPU and load/execute/debug C/Rust core with it and control the peripherals of the board.
LiteX based FPGA SoC designed for the Siglent SDS1104X-E oscilloscope, providing an open-source implementation to enhance and extend the scope's functionality.
LiteX based FPGA SoC for the ThunderScope Scope.
The Colorlight 5A-75B is an inexpensive (15$) led control board equipped with a Lattice ECP5 FPGA, 2 x 1Gbps Ethernet and lots of IOs. ColorLite project explains how to create a cheap remote control/monitoring system with it can be useful to discover LiteX/LiteEth through a practical example.
The iCEBreaker is the first open source iCE40 FPGA development board designed for teachers and students. The iCEBreaker target integrated in LiteX-Boards provides a minimal LiteX SoC for the iCEBreaker with a CPU, its ROM (in SPI Flash), its SRAM, close to the others LiteX targets. A more complete example of LiteX SoC for the iCEBreaker with more features, examples to run C/Rust code on the RISC-V CPU and documentation can be found in the iCEBreaker LiteX examples tutorial.
Blogpost/Wiki by @bunnie from 2018 with his understanding of LiteX and tips for engineers with a hardware background.
Wiki of LiteX Buildenv project with information complementary to LiteX's Wiki.
Blogpost by gojimmypi testing LiteX on the ULX3S board and experimenting with the Soft CPU.
Tiny collection of tips for the Colorlight i5 FPGA board.
Use of the SQRL Acorn with LitePCIe in a Thunderbolt/nVME enclosure.
Discovery/Use of LiteX with FemtoRV CPU by @BrunoLevy.
Discovery of LiteX as a SoC Builder by @controlpaths
Librecar is an automotive exploration tool focused on vehicle protocol emulation and data handling, using low-cost FPGA to manage CANbus.
A project running dual-core 32-bit RISC-V Linux on the affordable Sipeed Tang Primer FPGA board, describing changes done to Linux-on-LiteX-VexRiscv project.
Have a question or want to get in touch? Our IRC channel is #litex at irc.libera.chat.
- Welcome to LiteX
- LiteX's internals
- How to
- Create a minimal SoC-TODO
- Add a new Board-TODO
- Add a new Core-WIP
- Add a new CPU-WIP
- Reuse-a-(System)Verilog,-VHDL,-Amaranth,-Spinal-HDL,-Chisel-core
- Use LiteX on the Acorn CLE 215+
- Load application code the CPU(s)
- Use Host Bridges to control/debug a SoC
- Use LiteScope to debug a SoC
- JTAG/GDB Debugging with VexRiscv CPU
- JTAG/GDB Debugging with VexRiscv-SMP, NaxRiscv and VexiiRiscv CPUs
- Document a SoC
- How to (Advanced)