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Cores Ecosystem
enjoy-digital edited this page Aug 1, 2023
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Welcome to the LiteX Cores Ecosystem, a comprehensive repository of diverse hardware-oriented cores designed to meet your development needs. From Dynamic RAM control with LiteDRAM, Ethernet capabilities with LiteEth, to PCIe support with LitePCIe, we offer a wide array of tools.
Our ecosystem also includes LiteSATA, LiteSDCard, LiteICLink, LiteJESD204B, LiteSPI, LiteHyperBus, and LiteScope, each serving specialized functions. To understand more about each core's build status, supported standards, and hardware compatibility, please refer to the tables below. Your journey into efficient and advanced hardware development starts here!
LiteDRAM | |
---|---|
Build Status | |
Description | Dynamic RAM controller |
Supported Standards | SDRAM, (LP)DDR, DDR2, DDR3, (LP)DDR4. |
Supported Hardware | Generic, Xilinx Spartan-6 / 7-Series / Utrascale(+), Lattice ECP5. |
LiteEth | |
---|---|
Build Status | |
Description | Ethernet |
Supported Standards | 100/1000Mbps, MII/GMII/RGMII/1000Base-X. |
Supported Hardware | Generic, Xilinx Spartan-6 / 7 Series / Ultrascale(+), Lattice ECP5. |
LitePCIe | |
---|---|
Build Status | |
Description | PCIe |
Supported Standards | Gen1/2/3, X1 to X16. |
Supported Hardware | Xilinx 7-Series/Ultrascale(+), Intel Cyclone V. |
LiteSATA | |
---|---|
Build Status | |
Description | SATA |
Supported Standards | 1.5/3.0/6.0 GBps |
Supported Hardware | Xilinx 7-Series/Ultrascale(+). |
LiteSDCard | |
---|---|
Build Status | |
Description | SD Card |
Supported Standards | SD / SDHC / SDXC / SDUC, Default Speed, High Speed, UHS-I |
Supported Hardware | Generic. |
LiteICLink | |
---|---|
Build Status | |
Description | Inter-Chip communication |
Supported Standards | Raw communication over Single Ended/LVDS Pair/Transceivers. |
Supported Hardware | Generic, Xilinx 7-series/Ultrascale(+), Lattice ECP5. |
LiteJESD204B | |
---|---|
Build Status | |
Description | JESD204B |
Supported Standards | |
Supported Hardware | Xilinx 7-series/Ultrascale(+). |
LiteSPI | |
---|---|
Build Status | |
Description | SPI/(Q)SPI Flash |
Supported Standards | |
Supported Hardware | Generic. |
LiteHyperBus | |
---|---|
Build Status | |
Description | HyperBus/HyperRAM |
Supported Standards | |
Supported Hardware | Generic |
LiteScope | |
---|---|
Build Status | |
Description | Embedded FPGA logic analyzer |
Supported Standards | PCIe, UART, Ethernet. |
Supported Hardware | Generic. |
Have a question or want to get in touch? Our IRC channel is #litex at irc.libera.chat.
- Welcome to LiteX
- LiteX's internals
- How to
- Create a minimal SoC-TODO
- Add a new Board-TODO
- Add a new Core-WIP
- Add a new CPU-WIP
- Reuse-a-(System)Verilog,-VHDL,-Amaranth,-Spinal-HDL,-Chisel-core
- Use LiteX on the Acorn CLE 215+
- Load application code the CPU(s)
- Use Host Bridges to control/debug a SoC
- Use LiteScope to debug a SoC
- JTAG/GDB Debugging with VexRiscv CPU
- JTAG/GDB Debugging with VexRiscv-SMP, NaxRiscv and VexiiRiscv CPUs
- Document a SoC
- How to (Advanced)