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Streams
Jevin Sweval edited this page Jun 25, 2022
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LiteX's streams are group of signals (Migen's Record) used to create Sink/Source Endpoints on Modules and easily transfer data between them. LiteX's streams are a simplified compromise between AXI-4/Avalon-ST:
-
valid
: similar to AXI-4'stvalid
. -
ready
: similar to AXI-4'stready
. -
first
(used for packets only when needed): similar to Avalon-ST'ssop
, because it's sometimes useful to just easily know the start of a packet instead of deducing it from last as done in AXI-4. -
last
(used for packets) : similar to AXI-4'slast
. -
payload
: a Record with its own layout, similar to AXI-4'stdata
that can evolve at each valid/ready transaction. -
param
(optional): a Record with its own layout, similar to AXI-4'stuser
that can evolve at each start of packet.
LiteX's streams can be directly mapped to AXI-4 and adapted easily to AvalonST with: https://github.com/enjoy-digital/litex/blob/master/litex/soc/interconnect/avalon.py.
alanvgreen has provided a thorough description of LiteX streams and a helpful diagram.
Have a question or want to get in touch? Our IRC channel is #litex at irc.libera.chat.
- Welcome to LiteX
- LiteX's internals
- How to
- Create a minimal SoC-TODO
- Add a new Board-TODO
- Add a new Core-WIP
- Add a new CPU-WIP
- Reuse-a-(System)Verilog,-VHDL,-Amaranth,-Spinal-HDL,-Chisel-core
- Use LiteX on the Acorn CLE 215+
- Load application code the CPU(s)
- Use Host Bridges to control/debug a SoC
- Use LiteScope to debug a SoC
- JTAG/GDB Debugging with VexRiscv CPU
- JTAG/GDB Debugging with VexRiscv-SMP, NaxRiscv and VexiiRiscv CPUs
- Document a SoC
- How to (Advanced)