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Run MicroPython CircuitPython On Your SoC
You can find the LiteX MicroPython port at: https://github.com/litex-hub/micropython/tree/litex-rebase
This is a port of MicroPython to the LiteX SoC FPGA framework. LiteX allows easy creation of SoCs on FPGAs and use of various CPU ISAs/Implementations (VexRiscv, Mor1kx, LM32) and peripherals. By combining the flexibility of LiteX to define the hardware and the flexibility of MicroPython to control it, very powerful and flexible systems can be created!
Supported features:
- REPL (Python prompt) over UART.
- Minimal umachine support (reset, freq, identifier).
- Minimal litex support(leds, switches).
To install LiteX, please follow the LiteX installation guide.
The port of MicroPython to LiteX relies on the software files generated during the target build that will provides the hardware definition and mapping to MicroPython. To build the MicroPython firmware, the LiteX target then first needs to be generated. Many FPGA boards are already available in LiteX-Boards, in this example, we'll use the Digilent Arty board:
$ python3 -m litex_boards.targets.digilent_arty --with-ethernet --with-pmod-gpio --build --load
This will build the FPGA SoC, generate the software headers, compile the BIOS/FPGA and load it to the board.
To build MicroPython for your LiteX target run:
$ export BUILD_DIRECTORY=build/digilent_arty
$ make
To load MicroPython for your LiteX target run:
$ litex_term /dev/ttyUSBX --kernel=build/firmware.bin
You can also use TFTP boot from LiteX:
$ cp build/firmware.bin /tftpboot/boot.bin
And just let LiteX boot from it!...
..or use one of the other available boot methods described at https://github.com/enjoy-digital/litex/wiki/Load-Application-Code-To-CPU
Have a question or want to get in touch? Our IRC channel is #litex at irc.libera.chat.
- Welcome to LiteX
- LiteX's internals
- How to
- Create a minimal SoC-TODO
- Add a new Board-TODO
- Add a new Core-WIP
- Add a new CPU-WIP
- Reuse-a-(System)Verilog,-VHDL,-Amaranth,-Spinal-HDL,-Chisel-core
- Use LiteX on the Acorn CLE 215+
- Load application code the CPU(s)
- Use Host Bridges to control/debug a SoC
- Use LiteScope to debug a SoC
- JTAG/GDB Debugging with VexRiscv CPU
- JTAG/GDB Debugging with VexRiscv-SMP, NaxRiscv and VexiiRiscv CPUs
- Document a SoC
- How to (Advanced)