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Copyright 2012-2020 / Enjoy-Digital
LiteX is a Migen/MiSoC based Core/SoC builder that provides the infrastructure to easily create Cores/SoCs (with or without CPU). The common components of a SoC are provided directly: Buses and Streams (Wishbone, AXI, Avalon-ST), Interconnect, Common cores (RAM, ROM, Timer, UART, etc...), CPU wrappers/integration, etc... and SoC creation capabilities can be greatly extended with the ecosystem of LiteX cores (DRAM, PCIe, Ethernet, SATA, etc...) than can be integrated/simulated/build easily with LiteX. It also provides build backends for open-source and vendors toolchains.
Think of Migen as a toolbox to create FPGA designs in Python and LiteX as a SoC builder to create/develop/debug FPGA SoCs in Python.
A question or want to get in touch? Our IRC channel is #litex at freenode.net
+---------------+
|FPGA toolchains|
+----^-----+----+
| |
+--+-----v--+
+-------+ | |
| Migen +--------> |
+-------+ | | Your design
| LiteX +---> ready to be used!
| |
+----------------------+ | |
|LiteX Cores Ecosystem +--> |
+----------------------+ +-^-------^-+
(Eth, SATA, DRAM, USB, | |
PCIe, Video, etc...) + +
board target
file file
LiteX already supports various softcores CPUs: VexRiscv, Rocket, LM32, Mor1kx, PicoRV32 and is compatible with the LiteX's Cores Ecosystem:
Name | Build Status | Description |
---|---|---|
LiteDRAM | DRAM | |
LiteEth | Ethernet | |
LitePCIe | PCIe | |
LiteSATA | SATA | |
LiteSDCard | SD card | |
LiteICLink | Inter-Chip communication | |
LiteJESD204B | JESD204B | |
LiteVideo | VGA, DVI, HDMI | |
LiteScope | Logic analyzer |
Combining LiteX with the ecosystem of cores allows the creation of complex SoCs such as the one below created for the NeTV2 board to do HDMI capture/playback over PCIe:
FPGA lessons/tutorials:
Migen tutorial:
OSDA 2019 paper/slides:
Linux on LiteX-Vexriscv:
RISC-V Getting Started Guide:
LiteX vs. Vivado First Impressions:
35C3 - Snakes and Rabbits - How CCC shaped an open hardware success:
Tim has to many projects - LatchUp Edition: https://www.youtube.com/watch?v=v7WrTmexod0
litex.gen Provides specific or experimental modules to generate HDL that are not integrated in Migen.
litex.build: Provides tools to build FPGA bitstreams (interface to vendor toolchains) and to simulate HDL code or full SoCs.
litex.soc: Provides definitions/modules to build cores (bus, bank, flow), cores and tools to build a SoC from such cores.
litex.boards: Provides platforms and targets for the supported boards. All Migen's platforms can also be used in LiteX. The boards present in the LiteX repository are the official ones that are used for development/CI. More boards are available at: https://github.com/litex-hub/litex-boards
- Install Python 3.5+ and FPGA vendor's development tools.
- Install Migen/LiteX and the LiteX's cores:
On MacOS, make sure you have HomeBrew installed. Then do, brew install wget
.
$ wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py
$ chmod +x litex_setup.py
$ ./litex_setup.py init install --user (--user to install to user directory)
Later, if you need to update all repositories:
$ ./litex_setup.py update
- Install a RISC-V toolchain:
$ ./litex_setup.py gcc
-
Build the target of your board...: Go to litex-boards/litex_boards/xxyy/targets (xxyy being community/official/partner) and execute the target you want to build
-
... and/or install Verilator and test LiteX on your computer
On Fedora:
$ sudo dnf install libevent-devel json-c-devel
On Ubuntu:
$ sudo apt install libevent-dev libjson-c-dev verilator
$ litex_sim
On MacOS:
$ brew install json-c verilator libevent
$ brew cask install tuntap
$ litex_sim
- Run a terminal program on the board's serial port at 115200 8-N-1.
You should get the BIOS prompt like the one below.
LiteX has been initially developed by EnjoyDigital to create custom SoCs/Systems for our clients (and we are still using it for that purpose :)); but over the years a friendly community has grown around LiteX and the ecosystem of cores. Feedbacks and contributions have already greatly improved the project, EnjoyDigital still leads the development but it is now a community project and collaborative projects created around/with LiteX can be found at https://github.com/litex-hub.
E-mail: florent@enjoy-digital.fr
Have a question or want to get in touch? Our IRC channel is #litex at irc.libera.chat.
- Welcome to LiteX
- LiteX's internals
- How to
- Create a minimal SoC-TODO
- Add a new Board-TODO
- Add a new Core-WIP
- Add a new CPU-WIP
- Reuse-a-(System)Verilog,-VHDL,-Amaranth,-Spinal-HDL,-Chisel-core
- Use LiteX on the Acorn CLE 215+
- Load application code the CPU(s)
- Use Host Bridges to control/debug a SoC
- Use LiteScope to debug a SoC
- JTAG/GDB Debugging with VexRiscv CPU
- JTAG/GDB Debugging with VexRiscv-SMP, NaxRiscv and VexiiRiscv CPUs
- Document a SoC
- How to (Advanced)