This pass attempts to merge s_buffer_load_dword instructions into larger
sizes.
Constraints are that the resource descriptor, glc flag and size are all the same
for contiguous load instructions.

TODO: it should be possible to add different instructions to this as well such
as s_buffer_store and the vector variants buffer_load/buffer_store

V2: Fixes to sbuff-merge test
V3: Fixed smrd test for smem merging
V4: Fixed for gfx10 changes

Change-Id: Ie98107ad3b27b3c8c2da7afc3d129336f924895a

Summary:
Added intrinsics for the instructions:
- buffer_load_ubyte
- buffer_load_ushort
- buffer_store_byte
- buffer_store_short

Added test cases to existing buffer load/store tests.

Now that upstream supports byte/short overloads of the normal load/store
intrinsics, this change is only needed until LLPC stops using the
intrinsics added here.

Change-Id: I1b8a0910c508c9520a84b74a14d0aea8293cef38

Vulkan exposed an issue with this for a case with v_mad_mixlo_f16 where the
upper 16 bits were not cleared.

Modifying this to clear the bits instead of just copying fixed the problem.

V2: Fixed up "Fix issue for zext of f16 to i32"
V3: Fixed fcanonicalize-elimination test

Change-Id: I6128deaf8ebc3489fdd3e0caead837410bb47160

Readlane should have a uniform index - but in some cases it can be non-uniform.
The original implementation of readlane defaulted to using a readfirstlane of
the vgpr index on the assumption that the index would be uniform across all
lanes.

However, there are some cases where we might want a readlane like operation that
is lowered to a waterfall that performs a readlane for each distinct index value
across lanes.

Essentially we form a loop that uses readfirstlane to get the first enabled
lane's index - enable all lanes with the same index, perform a readlane and put
the result into the vgpr result register, then disable those lanes and repeat.

The pathological case will form a loop of 64 - but in most cases it will be
fewer.
In the case where the index IS uniform across all lanes, it will loop once,
which is slightly more expensive than the original code, but not a lot more.

V2: Initialize accumulator register in waterfall code
V3: Fixed for gfx10 changes

Change-Id: Ic52dfb14b053db7713b61c85e8ac766991aecdb8

Even though writelane doesn't have the same constraints as other valu
instructions it still can't violate the >1 SGPR operand constraint

Due to later register propagation (e.g. fixing up vgpr operands via
readfirstlane) changing writelane to only have a single SGPR is tricky.

This implementation puts a new check after SIFixSGPRCopies that prevents
multiple SGPRs being used in any writelane instructions.

The algorithm used is to check for trivial copy prop of constants into one of
the SGPR operands and perform that if possible. If this isn't possible put an
explicit copy of Src1 SGPR into M0 and use that instead (this is allowable for
writelane as the constraint is for SGPR read-port and not constant-bus access).

V2: Fix-up cases where writelane has 2 SGPR operands - bug fixes

Update to previous commit to fix an issue where immediates are tested for copy
propagation but aren't suitable as inline constants. The old method caused
issues that resulted in seg faults in later cse phases.

Even though writelane doesn't have the same constraints as other valu
instructions it still can't violate the >1 SGPR operand constraint

Due to later register propagation (e.g. fixing up vgpr operands via
readfirstlane) changing writelane to only have a single SGPR is tricky.

This implementation puts a new check after SIFixSGPRCopies that prevents
multiple SGPRs being used in any writelane instructions.

The algorithm used is to check for trivial copy prop of constants into one of
the SGPR operands and perform that if possible. If this isn't possible put an
explicit copy of Src1 SGPR into M0 and use that instead (this is allowable for
writelane as the constraint is for SGPR read-port and not constant-bus access).

Change-Id: Ic3045df22db738ca6572af00138520fd28563990

Implements 3 new intrinsics for implementing waterfall code for regions of code.

Waterfall is implemented as a loop that iterates over an index of values for
active lanes. For each iteration an index is picked (the first active lane) and
all lanes with the same index are left active (the rest are disabled).
The body of the code is then executed and the result accumulated into a result
vector register.
The active lane is then disabled and the next index chosen for the next
iteration.

The worst case for waterfall is one iteration per lane - but it is usually far
less than this.

The implementation uses 3 intrinsics to mark a region:
  - llvm.amdgcn.waterfall.begin
  - llvm.amdgcn.waterfall.readfirstlane
  - llvm.amdgcn.waterfall.end

The group must contain one begin and at least one readfirstlane and end
intrinsic - if the readfirstlane uses the begin index, then there will only be a
single readfirstlane and not 2.

The readfirstlane and end intrinsics are not limited to single dword values.

The waterfall loop will enclose all instructions from the begin to the final end
intrinsic.

See the test case for specific examples of use.

V2:
[AMDGPU] Updates to waterfall intrinsic support

Some fixes for waterfall support.
1. Intrinsics are better defined so enforce type correctness
2. Creation of the waterfall loop requires removing kill flag for operands moved
into the loop, this can otherwise cause an assert during verification
3. Fixed issue causing a tablegen failure due to float return type being used
for a scalar return value (incorrectly). The matching for intrinsic to pseudo
instruction now uses 2 template parameter types to disambiguate when using float
src types.
4. Ensure that any analyses are invalidated due to insertion of new basic
blocks. This should have been the default anyway.
5. Updated test in light of these changes. These are good exemplars for
implementors to check against.

V3:
[AMDGCN] Fixed waterfall intrinsic groups for multiple groups per BB

For cases with more than one waterfall group per basic block, the implementation
would go wrong after creating the first waterfall loop (incorrectly tracking
current BB).

Also added a test case.

V4:
[AMDGCN] Waterfall enhancements

Extra waterfall test for multiple readfirstlane intrinsics. Make sure that the
waterfall intrinsic clauses support multiple readfirstlane intrinsics.

Extended support for begin to allow multi-dword indices for the waterfall
loop. This allows the use of multiple indexes (and multiple non-uniform values)
in the same waterfall loop by combining the individual indices into a single
multi-dword index.
This has the same worst-case of 64 iterations (wave size) as before.

Added a new test case to demonstrate using multi-dword indices.

Added support for i16/f16

Changed the implementation to prevent CSE from merging clauses (by tagging the
intrinsics as having side effects and enhancing uniform detection to work in
this case as well).
Left in some support added to partially support EarlyCSE merging as it is still
valid, but probably won't be triggered much now merging is disabled.

Added support for a last.use intrinsic. See the test for an example of
this. This works in the same way as the end intrinsic, but you tag a last_use
instead (so it includes the next use in the waterfall loop). More than one use
is acceptable as long as it is in the same BB. All instructions up to the last
last.use will be included in the waterfall loop.

An important rule for waterfall clauses (that isn't detected if violated) is
that you can't have something inside the loop that is dependent on an end
intrinsic in the loop - this restriction is logically consistent - you have to use
two loops instead.

V5:
[AMDGPU] Handle unexpected uniform inputs in waterfall intrinsics

Waterfall intrinsic input operands can sometimes be uniform. The waterfall
handling pass should deal with this gracefully, even though this could be
sub-optimal.

This is an initial fix for a problem observed in a game.
Subsequent better fix being worked on which should produce optimal code (by
removing redundant waterfall loops entirely if all the elements turn out to be
uniform anyway).

V6:
[AMDGPU] Improved handling of uniform waterfalls

This builds on a previous fix for uniform values being specified in waterfall
loop intrinsic groups.
Previous fix would just remove any waterfall.readfirstlane intrinsics if the
input was uniform.

This fix improves on this by spotting when ALL waterfall.readfirstlanes are
uniform and removing the waterfall loop entirely.

The tests have been extended to test this mode.

The update also handles the case where not all waterfall.readfirstlanes are
removed. This is also covered in the associated tests.

V7:
[AMDGCN] Re-order waterfall and wholequadmode passes

Running WholeQuadMode pass after waterfall can have bad consequences.
Changing the order improves the outcome - but there may still be problems in
some unusual cases.
For the known uses of the waterfall intrinsics this change will work for now.

V8:
waterfall test fixup

Change-Id: I95b4391b8c0570bd399d70ed64af355d13ef4c84

Summary:
The test shows a case where a full use is not in a subrange because the
subreg is undefined at the use point, but, after a coalesce, the
subrange incorrectly still does not include the use even though the
subreg is now defined at that point. The incorrect live range causes a
"subrange join unreachable" assert on a later coalesce.

This commit ensures that a subrange is extended to all uses that can be
reached from a definition.

V2: Completely different fix, instead of working round the problem in
the later coalesce that actually asserted.
V5: Fixed to not extend liveness to an undef use. Spun second test out
into its own D51257 as it is a completely different problem with the
same "subrange join unreachable" symptom.
V6: Ignore debug uses.
V7: Set up undefs correctly, to avoid generating invalid subranges.

Differential Revision: https://reviews.llvm.org/D49097

Change-Id: I172cfe16d360690e921ebe606d3e90dd1cdd1b71

eliminateUndefCopy was incorrectly eliminating a copy that was only a
partial write of the target. In the test case, the resulting incorrect
live range caused a subrange join unreachable later.

The test case does not fail for me until I have D49097.

Differential Revision: https://reviews.llvm.org/D51257

Change-Id: Ibb767d8a016934431660764b0194634e2113fea2

Summary:
findReachingDefs was incorrectly using its fast path of just blitting in
the live range extension when it did not see an undef itself but
encountered an undef live out of a predecessor block.

Now RegisterCoalescing calls extendToIndices (D49097), the bug was
causing an incorrect subrange which led to a "Couldn't join subrange!"
assert in a later coalesce.

Subscribers: MatzeB, jvesely, nhaehnle, llvm-commits

Differential Revision: https://reviews.llvm.org/D51574

Change-Id: I01c942b41ab5a145348289c8b221c45a2ec7200f

…vePartialRedundancy

Summary:
removePartialRedundancy was using extendToIndices on each subrange
without passing in an Undefs vector containing main reg defs that are
undef in the subrange, causing the above assert.

Unfortunately I can only reproduce this in an ll test. Turning it into a
mir test makes the problem go away.

Subscribers: MatzeB, qcolombet, jvesely, nhaehnle, llvm-commits

Differential Revision: https://reviews.llvm.org/D51849

Change-Id: I4f3ba2afb20d79f9467afb3d882f0328d38531be

…wCopyChain

valuesIdentical is called to determine whether a def can be considered
an "identical erase" because following copy chains proves that the value
being copied is the same value as the value of the other register.

The tests show up problems where the main range decides that a def is
an "identical erase" but a subrange disagrees, because following the
copy chain leads to a def that does not define all subregs in the
subrange (in the case of one test) or a different def to that found in
the main range (in the case of the other test).

The fix here is to only detect an "identical erase" in the main range.
If it is found, it is automatically inherited by the corresponding def
in any subrange, without further analysis of that subrange value.

This fix supersedes D49535/rL338070 and D51848.

Change-Id: I059b5b2273ed6f186d134b98c118fef0494e02f8

This is a temporary fix to avoid a breakage where the export(s) for a
pixel shader are in control flow (due to a kill). A pixel shader must
execute an export done, even with exec=0.

A better fix would be to have a pixel-shader-only pass that inserts a
null export done in the final basic block if there is not one already
there.

Change-Id: I22f201f95d52ff699aa8cac26bb019717b20432e

LLPC has .ll file library functions that break this verifier check. We
need to fix those before re-enabling the check.

Change-Id: I4c000793a805a50f1d91d1ae55c567a356e72519

This commit fixes a really fun bug with inst combine where you have a
vector-of-pointers and only one element of this vector is used.
InstCombine correctly notes that an element is not used, and then will
go back through a gep into that vector-of-pointers and set all vector
elements to undef. This is fine in all cases except that the langref
(and a ton of places in the optimizer) requires that indexing into a
struct has the same index for each element of the vector-of-pointers.

To fix the bug I've just made the gep/undef propagation check that the
current type being indexed into is not a struct when doing the undef
propagation.

Differential Revision: https://reviews.llvm.org/D60600

Change-Id: I6eba34b1cde9c14751c39f04627e39425639ab3b

…d non-divergent

Summary:
This fixes an issue where values are uniform inside of a loop but
the uses of that value outside the loop can be divergent.

This is a temporary fix until the library linker issues can be resolved
in llvm.

Change-Id: I94d3d2e30cc2a6ae8d59e92cadf6f1b6cb7e708b

Implement a pass, enabled by -amdgpu-scratch-bounds-checking,
or the subtarget feature "enable-scratch-bounds-checks",
which adds bounds checks to scratch accesses.
When this pass is enabled, out-of-bounds writes have no effect
and out-of-bounds reads return zero.
This is useful for GFX9 where hardware no longer performs
bounds checking on scratch accesses and hence page faults
result for out-of-bounds accesses by generated by shaders.

Change-Id: Id2ee4b1f32e70b6bde2541db755727b6a407721b

stripValuesNotDefiningMask was asserting that it did not leave an empty
subrange. However that was bogus because the subrange could have been
empty to start with, in the case that LiveRangeCalc::calculate saw a
subreg use that caused a subrange to be created empty.

Differential Revision: https://reviews.llvm.org/D63510

Change-Id: Ibf862415ea422198975cc7a2ca2d98531beec08d

…REL_OFFSET is 0"

This reverts commit 58b3837.

That commit was causing an unnecessary reloc when accessing a global in
the same section. On PAL, that breaks our use of a read-only global
variable as an optimization of a local variable with constant
initialization, because the PAL loader ignores the reloc.

Change-Id: I2792404227d08d98baee69504509828de7e9b36c

Implement appropriate register allocation and exec mask usage
for wave32 scenarios.

Change-Id: I844018f6c07fdda46366af51654017fb4b654d8a

Extended test to check wave32 and gfx10

Change-Id: I620c6d9e737ddccdfd3494abf72632d7ecc4a53f

Change-Id: I3557477344135f7dbece33a2945bcb9f4063c10f

Extend LoadStoreOptimizer to handle IMAGE_LOAD and IMAGE_SAMPLE.

Change-Id: Id49c992b9781254e39e1352125f5ffb212fe4f24

Summary:
Backend defaults to setting WGP mode to 0 or 1 depending on the cumode
feature. For PAL clients we want PAL to set this mode.
Adding check to prevent the backend overriding whatever the front end has set.

Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, tpr, t-tye, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63639

Change-Id: Ia3bac3e562fb47089f05c11cae47d1c92f7195ee

Fix a breakage in areMemAccessesTriviallyDisjoint, caused
by trying to merge a non-load MIMG instruction IMAGE_GET_RESINFO.

Only MIMG that loads from memory should be considered.

Change-Id: I012435534b3e6161ee7feb686d4711097d2ab980

Currently the atomic optimizer does not support wave32,
and may generate DPP which is incompatible with GFX10.
This change allows the atomic optimizer to be enabled
unconditionally by the LLPC for all ASICs.

Change-Id: Ia26b527675b6e07319f4299b3f82ad405916bad6

Summary:
This fixes B42473 and B42706.

This patch makes the SDA propagate branch divergence until the end of the RPO traversal. Before, the SyncDependenceAnalysis propagated divergence only until the IPD in rpo order. RPO is incompatible with post dominance in the presence of loops. This made the SDA crash because blocks were missed in the propagation.

Reviewers: foad, nhaehnle

Subscribers: jvesely, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D65274

Change-Id: Ic3fcc51e5850fde3a4649ec3dd84a040a07aaca9

Summary:
Add support for gfx10, where all DPP operations are confined to work
within a single row of 16 lanes, and wave32.

Reviewers: arsenm, sheredom, critson, rampitec

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, t-tye, hiraditya, jfb, dstuttard, tpr, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D65644

Change-Id: I1f8991e9cf732e79a139e79e70a2bf62650693d4

…DD_REL_OFFSET is 0"

This reverts commit ad3ea6fe0eedc9fe48b96453cfed51f8c1dd79de.

…ord in SI_PC_ADD_REL_OFFSET is 0"

(From Jay)

D61491 caused us to use relocs when they're not strictly necessary, to
refer to symbols in the text section. This is a pessimization and it's a
problem for some loaders that don't support relocs yet.

Differential Revision: https://reviews.llvm.org/D65813

Change-Id: Ia84de963ad099b7d2fcfb9cd2b908fa2e5a4788b

Change-Id: I3dddc18d5dea0fd1050633e35d0ac463a9ed26ca

That change (r363670) could leave a copy from vgpr to sgpr. Fixed.

Differential Revision: https://reviews.llvm.org/D66133

Change-Id: I00c3fe6fda2e8e1e36f53195b881b1449c777ea4

This reverts D64766.

That change caused me a problem where an LDS instruction was missing its
m0 initialization on gfx7 on a Vulkan CTS test on the GPUOpen driver.
Compiling the same code with llc on the upstream LLVM that our Vulkan
branch is based on did not show the problem. This needs further
investigation.

Change-Id: I94b380f60b074a117075ae12d15ae4babbc8c7af

Summary: Add missing tbuffer loads intrinsics in SimplifyDemandedVectorElts.

Reviewers: arsenm, nhaehnle

Reviewed By: arsenm

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D66926

Change-Id: I63f53e8cd45f2e3683d109fb7624ba04eac365e7
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370475 91177308-0d34-0410-b5e6-96231b3b80d8

Configure TLI to say that r600/amdgpu does not have any library
functions, such that InstCombine does not do anything like turn sin/cos
into the library function @tan with sufficient fast math flags.

Differential Revision: https://reviews.llvm.org/D67406

Change-Id: I02f907d3e64832117ea9800e9f9285282856e5df

Summary:
This propagates a sgpr->vgpr copy into an operand of a
v_fma/v_mad that is generated from v_fmac, given it
doesn't break constant bus restriction

Change-Id: I39cacf43205e15982f7405c805d67b7a8b11d2a9

This reverts commit eb43d3e.

Change-Id: I3d2e12c87aa3dd6ecae9115832635381c67177b7

We had test problems with this. It will be reinstated as soon as a fix
is identified.

This reverts commit d14be0a652cb943bea16919e8542f00348c36586.

Change-Id: Icb4d534e5bfec37e740707cbd6d860bbd1ec53f3

Temporarily reverting this as it has missed most of the testing cycle.

This reverts commit 560afd3c65a73d0b06badbb19d6e5b0a4414bee5.

Change-Id: Idafd4baaf6f4440c64f39182942973affe881cce

…fer loads"

Based on upstream llvm 368122: 989679c Reverts commit r368117, r368115 and r368112

Added AMD modification notices and removed non-LLVM directories and some GPL files.

This pass attempts to merge s_buffer_load_dword instructions into larger
sizes.
Constraints are that the resource descriptor, glc flag and size are all the same
for contiguous load instructions.

TODO: it should be possible to add different instructions to this as well such
as s_buffer_store and the vector variants buffer_load/buffer_store

V2: Fixes to sbuff-merge test
V3: Fixed smrd test for smem merging
V4: Fixed for gfx10 changes

Change-Id: Ie98107ad3b27b3c8c2da7afc3d129336f924895a

Summary:
Added intrinsics for the instructions:
- buffer_load_ubyte
- buffer_load_ushort
- buffer_store_byte
- buffer_store_short

Added test cases to existing buffer load/store tests.

Now that upstream supports byte/short overloads of the normal load/store
intrinsics, this change is only needed until LLPC stops using the
intrinsics added here.

Differential Revision: https://reviews.llvm.org/D42885

Change-Id: I1b8a0910c508c9520a84b74a14d0aea8293cef38

Vulkan exposed an issue with this for a case with v_mad_mixlo_f16 where the
upper 16 bits were not cleared.

Modifying this to clear the bits instead of just copying fixed the problem.

V2: Fixed up "Fix issue for zext of f16 to i32"
V3: Fixed fcanonicalize-elimination test

Differential Revision: https://reviews.llvm.org/D51925

Change-Id: I6128deaf8ebc3489fdd3e0caead837410bb47160

Even though writelane doesn't have the same constraints as other valu
instructions it still can't violate the >1 SGPR operand constraint

Due to later register propagation (e.g. fixing up vgpr operands via
readfirstlane) changing writelane to only have a single SGPR is tricky.

This implementation puts a new check after SIFixSGPRCopies that prevents
multiple SGPRs being used in any writelane instructions.

The algorithm used is to check for trivial copy prop of constants into one of
the SGPR operands and perform that if possible. If this isn't possible put an
explicit copy of Src1 SGPR into M0 and use that instead (this is allowable for
writelane as the constraint is for SGPR read-port and not constant-bus access).

V2: Fix-up cases where writelane has 2 SGPR operands - bug fixes

Update to previous commit to fix an issue where immediates are tested for copy
propagation but aren't suitable as inline constants. The old method caused
issues that resulted in seg faults in later cse phases.

Even though writelane doesn't have the same constraints as other valu
instructions it still can't violate the >1 SGPR operand constraint

Due to later register propagation (e.g. fixing up vgpr operands via
readfirstlane) changing writelane to only have a single SGPR is tricky.

This implementation puts a new check after SIFixSGPRCopies that prevents
multiple SGPRs being used in any writelane instructions.

The algorithm used is to check for trivial copy prop of constants into one of
the SGPR operands and perform that if possible. If this isn't possible put an
explicit copy of Src1 SGPR into M0 and use that instead (this is allowable for
writelane as the constraint is for SGPR read-port and not constant-bus access).

Differential Revision: https://reviews.llvm.org/D51932

Change-Id: Ic3045df22db738ca6572af00138520fd28563990

Implements 3 new intrinsics for implementing waterfall code for regions of code.

Waterfall is implemented as a loop that iterates over an index of values for
active lanes. For each iteration an index is picked (the first active lane) and
all lanes with the same index are left active (the rest are disabled).
The body of the code is then executed and the result accumulated into a result
vector register.
The active lane is then disabled and the next index chosen for the next
iteration.

The worst case for waterfall is one iteration per lane - but it is usually far
less than this.

The implementation uses 3 intrinsics to mark a region:
  - llvm.amdgcn.waterfall.begin
  - llvm.amdgcn.waterfall.readfirstlane
  - llvm.amdgcn.waterfall.end

The group must contain one begin and at least one readfirstlane and end
intrinsic - if the readfirstlane uses the begin index, then there will only be a
single readfirstlane and not 2.

The readfirstlane and end intrinsics are not limited to single dword values.

The waterfall loop will enclose all instructions from the begin to the final end
intrinsic.

See the test case for specific examples of use.

V2:
[AMDGPU] Updates to waterfall intrinsic support

Some fixes for waterfall support.
1. Intrinsics are better defined so enforce type correctness
2. Creation of the waterfall loop requires removing kill flag for operands moved
into the loop, this can otherwise cause an assert during verification
3. Fixed issue causing a tablegen failure due to float return type being used
for a scalar return value (incorrectly). The matching for intrinsic to pseudo
instruction now uses 2 template parameter types to disambiguate when using float
src types.
4. Ensure that any analyses are invalidated due to insertion of new basic
blocks. This should have been the default anyway.
5. Updated test in light of these changes. These are good exemplars for
implementors to check against.

V3:
[AMDGCN] Fixed waterfall intrinsic groups for multiple groups per BB

For cases with more than one waterfall group per basic block, the implementation
would go wrong after creating the first waterfall loop (incorrectly tracking
current BB).

Also added a test case.

V4:
[AMDGCN] Waterfall enhancements

Extra waterfall test for multiple readfirstlane intrinsics. Make sure that the
waterfall intrinsic clauses support multiple readfirstlane intrinsics.

Extended support for begin to allow multi-dword indices for the waterfall
loop. This allows the use of multiple indexes (and multiple non-uniform values)
in the same waterfall loop by combining the individual indices into a single
multi-dword index.
This has the same worst-case of 64 iterations (wave size) as before.

Added a new test case to demonstrate using multi-dword indices.

Added support for i16/f16

Changed the implementation to prevent CSE from merging clauses (by tagging the
intrinsics as having side effects and enhancing uniform detection to work in
this case as well).
Left in some support added to partially support EarlyCSE merging as it is still
valid, but probably won't be triggered much now merging is disabled.

Added support for a last.use intrinsic. See the test for an example of
this. This works in the same way as the end intrinsic, but you tag a last_use
instead (so it includes the next use in the waterfall loop). More than one use
is acceptable as long as it is in the same BB. All instructions up to the last
last.use will be included in the waterfall loop.

An important rule for waterfall clauses (that isn't detected if violated) is
that you can't have something inside the loop that is dependent on an end
intrinsic in the loop - this restriction is logically consistent - you have to use
two loops instead.

V5:
[AMDGPU] Handle unexpected uniform inputs in waterfall intrinsics

Waterfall intrinsic input operands can sometimes be uniform. The waterfall
handling pass should deal with this gracefully, even though this could be
sub-optimal.

This is an initial fix for a problem observed in a game.
Subsequent better fix being worked on which should produce optimal code (by
removing redundant waterfall loops entirely if all the elements turn out to be
uniform anyway).

V6:
[AMDGPU] Improved handling of uniform waterfalls

This builds on a previous fix for uniform values being specified in waterfall
loop intrinsic groups.
Previous fix would just remove any waterfall.readfirstlane intrinsics if the
input was uniform.

This fix improves on this by spotting when ALL waterfall.readfirstlanes are
uniform and removing the waterfall loop entirely.

The tests have been extended to test this mode.

The update also handles the case where not all waterfall.readfirstlanes are
removed. This is also covered in the associated tests.

V7:
[AMDGCN] Re-order waterfall and wholequadmode passes

Running WholeQuadMode pass after waterfall can have bad consequences.
Changing the order improves the outcome - but there may still be problems in
some unusual cases.
For the known uses of the waterfall intrinsics this change will work for now.

V8:
waterfall test fixup

Change-Id: I95b4391b8c0570bd399d70ed64af355d13ef4c84

Summary:
The test shows a case where a full use is not in a subrange because the
subreg is undefined at the use point, but, after a coalesce, the
subrange incorrectly still does not include the use even though the
subreg is now defined at that point. The incorrect live range causes a
"subrange join unreachable" assert on a later coalesce.

This commit ensures that a subrange is extended to all uses that can be
reached from a definition.

V2: Completely different fix, instead of working round the problem in
the later coalesce that actually asserted.
V5: Fixed to not extend liveness to an undef use. Spun second test out
into its own D51257 as it is a completely different problem with the
same "subrange join unreachable" symptom.
V6: Ignore debug uses.
V7: Set up undefs correctly, to avoid generating invalid subranges.

Differential Revision: https://reviews.llvm.org/D49097

Change-Id: I172cfe16d360690e921ebe606d3e90dd1cdd1b71

eliminateUndefCopy was incorrectly eliminating a copy that was only a
partial write of the target. In the test case, the resulting incorrect
live range caused a subrange join unreachable later.

The test case does not fail for me until I have D49097.

Differential Revision: https://reviews.llvm.org/D51257

Change-Id: Ibb767d8a016934431660764b0194634e2113fea2

Summary:
findReachingDefs was incorrectly using its fast path of just blitting in
the live range extension when it did not see an undef itself but
encountered an undef live out of a predecessor block.

Now RegisterCoalescing calls extendToIndices (D49097), the bug was
causing an incorrect subrange which led to a "Couldn't join subrange!"
assert in a later coalesce.

Subscribers: MatzeB, jvesely, nhaehnle, llvm-commits

Differential Revision: https://reviews.llvm.org/D51574

Change-Id: I01c942b41ab5a145348289c8b221c45a2ec7200f

…vePartialRedundancy

Summary:
removePartialRedundancy was using extendToIndices on each subrange
without passing in an Undefs vector containing main reg defs that are
undef in the subrange, causing the above assert.

Unfortunately I can only reproduce this in an ll test. Turning it into a
mir test makes the problem go away.

Subscribers: MatzeB, qcolombet, jvesely, nhaehnle, llvm-commits

Differential Revision: https://reviews.llvm.org/D51849

Change-Id: I4f3ba2afb20d79f9467afb3d882f0328d38531be

…wCopyChain

valuesIdentical is called to determine whether a def can be considered
an "identical erase" because following copy chains proves that the value
being copied is the same value as the value of the other register.

The tests show up problems where the main range decides that a def is
an "identical erase" but a subrange disagrees, because following the
copy chain leads to a def that does not define all subregs in the
subrange (in the case of one test) or a different def to that found in
the main range (in the case of the other test).

The fix here is to only detect an "identical erase" in the main range.
If it is found, it is automatically inherited by the corresponding def
in any subrange, without further analysis of that subrange value.

This fix supersedes D49535/rL338070 and D51848.

Differential Revision: https://reviews.llvm.org/D52061

Change-Id: I059b5b2273ed6f186d134b98c118fef0494e02f8

This is a temporary fix to avoid a breakage where the export(s) for a
pixel shader are in control flow (due to a kill). A pixel shader must
execute an export done, even with exec=0.

A better fix would be to have a pixel-shader-only pass that inserts a
null export done in the final basic block if there is not one already
there.

Change-Id: I22f201f95d52ff699aa8cac26bb019717b20432e

LLPC has .ll file library functions that break this verifier check. We
need to fix those before re-enabling the check.

Change-Id: I4c000793a805a50f1d91d1ae55c567a356e72519

…d non-divergent

Summary:
This fixes an issue where values are uniform inside of a loop but
the uses of that value outside the loop can be divergent.

This is a temporary fix until the library linker issues can be resolved
in llvm.

Differential Revision: https://reviews.llvm.org/D60834

Change-Id: I94d3d2e30cc2a6ae8d59e92cadf6f1b6cb7e708b

Implement a pass, enabled by -amdgpu-scratch-bounds-checking,
or the subtarget feature "enable-scratch-bounds-checks",
which adds bounds checks to scratch accesses.
When this pass is enabled, out-of-bounds writes have no effect
and out-of-bounds reads return zero.
This is useful for GFX9 where hardware no longer performs
bounds checking on scratch accesses and hence page faults
result for out-of-bounds accesses by generated by shaders.

Differential Revision: https://reviews.llvm.org/D60772

Change-Id: Id2ee4b1f32e70b6bde2541db755727b6a407721b

Extend LoadStoreOptimizer to handle IMAGE_LOAD and IMAGE_SAMPLE.

Change-Id: Id49c992b9781254e39e1352125f5ffb212fe4f24

Summary:
This fixes B42473 and B42706.

This patch makes the SDA propagate branch divergence until the end of the RPO traversal. Before, the SyncDependenceAnalysis propagated divergence only until the IPD in rpo order. RPO is incompatible with post dominance in the presence of loops. This made the SDA crash because blocks were missed in the propagation.

Reviewers: foad, nhaehnle

Subscribers: jvesely, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D65274

Change-Id: Ic3fcc51e5850fde3a4649ec3dd84a040a07aaca9

Add intrinsic which demotes all active lanes to helper lanes.
This is used to implement demote to helper vulkan extension.

In practice demoting a lane to helper simply means removing it
from the mask of live lanes used for WQM/WWM/Exact mode.
Where the shader does not use WQM demotes become kills.

To support this live lanes must now be tracked through entire
shader.  This involves adding PHI nodes during WQM pass,
which can expose exec mask change issues.  This is overcome
by split blocks on changes from WQM/WWM to Exact mode.
As a result the WQM pass no longer preserves CFG, slot indexes
or live intervals as these is no way of maintaining when blocks
are split.

Change-Id: I086fa95a1ba0880aa2799c0430242ecd02eb0a11

Based on upstream llvm 371856: b4160cb [ADT] Remove a workaround for old versions of clang

Local (non-upstream) changes since ccf09e1:
8e41591 [AMDGPU] Add llvm.amdgcn.wqm.demote intrinsic

Added AMD modification notices and removed non-LLVM directories and some GPL files.

Originally llvm.amdgcn.wqm.demote worked with llvm.amdgcn.ps.live;
however, this required changing the type signature of ps.live.
While the type signature of ps.live can be updated in LLPC,
other users such as Mesa should not be expected to change.

Change-Id: I7a18e7931bd7f2b4e0bfd4dc5718ff3718bb9d27

…ic to complement demote

Based on upstream llvm 371856: b4160cb [ADT] Remove a workaround for old versions of clang

Local (non-upstream) changes since ce9a97b:
4055769 [AMDGPU] Add llvm.amdgcn.wqm.helper intrinsic to complement demote

Added AMD modification notices and removed non-LLVM directories and some GPL files.

…n-uniform index

Based on upstream llvm 371856: b4160cb [ADT] Remove a workaround for old versions of clang

Local (non-upstream) changes since 0866736:
92b4e09 [AMDGPU] Use waterfall for readlane with non-uniform index
b9cf832 [AMDGPU] Allow FP inline constant in v_madak_f16 and v_fmaak_f16

Added AMD modification notices and removed non-LLVM directories and some GPL files.

… if no pow() lib func

Based on upstream llvm 371856: b4160cb [ADT] Remove a workaround for old versions of clang

Local (non-upstream) changes since 9d4e892:
56002f2 [SLC] Allow llvm.pow(x,2.0) -> x*x etc even if no pow() lib func

Added AMD modification notices and removed non-LLVM directories and some GPL files.

…f2 [NFC][ARM][MVE] More tests

Based on upstream llvm 373192: e3b4f0e [NFC][ARM][MVE] More tests

No local (non-upstream) changes since 6256c6e.

Added AMD modification notices and removed non-LLVM directories and some GPL files.

… broadcast load folding patterns to the NoVLX compare patterns.

Based on upstream llvm 373423: 8d6a863 [X86] Add broadcast load folding patterns to the NoVLX compare patterns.

Local (non-upstream) changes since 2b5181f:
e1d5296 Merge MIMG instructions
e0dc265 Revert "Merge MIMG instructions"

Added AMD modification notices and removed non-LLVM directories and some GPL files.

…scheduler

Based on upstream llvm 373958: 46d317f [Bitcode] Update naming of UNOP_NEG to UNOP_FNEG

Local (non-upstream) changes since 40fbaf4:
b19c164 Remove dubious logic in bidirectional list scheduler
8c7f063 Revert "[SimplifyCFG] FoldTwoEntryPHINode(): consider *total* speculation cost, not per-BB cost"
b24f8ac Revert "[AMDGPU] Run `unreachable-mbb-elimination` after isel to clean up PHIs."
2544d5d [LiveRangeCalc] Fixed findReachingDefs bug - test fixup
25e8457 Merge MIMG instructions
a1e75ec Revert "Merge MIMG instructions"
8c1a51e Revert "[AMDGPU] Use waterfall for readlane with non-uniform index"
35a70ca [AMDGPU] Remove waterfalls with dead readfirstlane intrinsics

Added AMD modification notices and removed non-LLVM directories and some GPL files.

…ssue export

Based on upstream llvm 374864: bbb8ead [Format] Add machine-readable SPDX license ID to clang-format.el

Local changes since 33e6f13:
acb3c7c Fixes after merge due to change to always issue export
aa25f98 Fix up tests based on changes to upstream and locally
bd63510 Merged upstream 374864: bbb8ead [Format] Add machine-readable SPDX license ID to clang-format.el
548c005 XFAIL after reversion [SimplifyCFG] FoldTwoEntryPHINode()
7938afb Merge "Update MIR tests" into amd-gfx
ba0a3d8 Fix local MIR tests after upstream merge changed sreg_128 -> sgpr_128
519f3c6 Update autogenerated test checks after recent merge from upstream.
93ff911 Merged from upstream llvm 374566: ee0a0a3 [AArch64][SVE] Implement sdot and udot (lane) intrinsics

Added AMD modification notices and removed non-LLVM directories and some GPL files.

…ng change for merge

Based on upstream llvm 375398: 3cc4835 Use Align for TFL::TransientStackAlignment

Local changes since 068af91:
b4d32d7 XFAIL dpp_combine.mir after reverting failing change for merge
33d8cd6 Revert "[AMDGPU] Allow DPP combiner to work with REG_SEQUENCE"
c5aefa7 Fixes for problems after upstream merge
fd005be Manual merge llvm.org master 375398: 3cc4835
ec94370 Revert "[AMDGPU] Fix-up cases where writelane has 2 SGPR operands"
556e5e3 Revert "Merge MIMG instructions"

Added AMD modification notices and removed non-LLVM directories and some GPL files.

…ross block values according to the divergence.'"

This reverts commit c4d256a.

Also xfailed three tests.

Change-Id: I6d301a01be105d1a93ef3b148cd8c1b852da7f25

This reverts commit eea1a46f3f4a2333380097682079ba2e28f88f4f.

Change-Id: I9ff5b491fe3764ca1498a9c1740771766a1dbed1

…g_128 for vregs"

Based on upstream llvm 374864: bbb8ead [Format] Add machine-readable SPDX license ID to clang-format.el

Local changes since 068af91:
6b257bf Revert "AMDGPU: Use SGPR_128 instead of SReg_128 for vregs"
717c9c6 Revert "[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'"

Added AMD modification notices and removed non-LLVM directories and some GPL files.

Change-Id: Ic5f917c4913614a2bd11c948025bac802edf2c7a

This reverts commit eea1a46f3f4a2333380097682079ba2e28f88f4f.

Change-Id: I9ff5b491fe3764ca1498a9c1740771766a1dbed1

…g_128 for vregs"

This is a branch off amd-gfx b4d32d7 XFAIL dpp_combine.mir after reverting failing change for merge
containing the reversion below.

Based on upstream llvm 375398: 3cc4835 Use Align for TFL::TransientStackAlignment

Local changes since 56636f1:
2c07340 Revert "AMDGPU: Use SGPR_128 instead of SReg_128 for vregs"

Added AMD modification notices and removed non-LLVM directories and some GPL files.

Change-Id: I73de8e6164feee31d59d1894a9e56e228ae41c73

This is to avoid a history break when moving from the branch with the
"Revert use SGPR_128" change back to mainline.

Change-Id: I87153683f22f6c0471d6820317e6ab8847dd07a9

…g_128 for vregs"

Based on upstream llvm : 08c7ff9 [libunwind] [Windows] Add a log message if EnumProcessModules fails

Local (non-upstream) changes since 65129cf:
3bbd3f1 Revert "AMDGPU: Use SGPR_128 instead of SReg_128 for vregs"
f91ccb0 Revert "Revert "[SimplifyCFG] FoldTwoEntryPHINode(): consider *total* speculation cost, not per-BB cost""
eb5facd [AMDGPU] Fix vccz after v_readlane/v_readfirstlane to vcc_lo/hi
654dede Revert "Revert "[AMDGPU] Allow DPP combiner to work with REG_SEQUENCE""
2817d90 Revert "XFAIL dpp_combine.mir after reverting failing change for merge"
42a79ae Revert "Revert "AMDGPU: Erase redundant redefs of m0 in SIFoldOperands""
4017707 Revert "Test fixups for reversion of Erase redundant redefs of m0 in SIFoldOperands"
736e7e8 Test fixups for reversion of Erase redundant redefs of m0 in SIFoldOperands
7c3184c Revert "AMDGPU: Erase redundant redefs of m0 in SIFoldOperands"

Added AMD modification notices and removed non-LLVM directories and some GPL files.

…0f5cabd

Based on upstream llvm : 0703db3 [CostModel] Fixed isExtractSubvectorMask for undef index off end

Local changes since 220194b:
d401164 Merged master:0703db39892 into amd-gfx:37ae0f5cabd
37ae0f5 Merged master:6bf9e88ae4a into amd-gfx:1b269b1013d
1b269b1 Merged master:41449c58c58 into amd-gfx:94d9f17da94
94d9f17 Merged master:0f88caeef8f into amd-gfx:fea644ea3cc
fea644e Merged master:bcf754a3212 into amd-gfx:2e774eed464
2e774ee Merged master:de61aa3118b into amd-gfx:1747a4ec9e6
1747a4e Merged master:9577ee84e63 into amd-gfx:76cd82d528c
76cd82d Merged master:6c3fee47a64 into amd-gfx:d1f949b785b
d1f949b Merged master:092452d402d into amd-gfx:9972ad51bc8
9972ad5 Merged master:bc496677d0e into amd-gfx:1f32295b917
1f32295 Merged master:39525a67238 into amd-gfx:3bbd3f1235f

Added AMD modification notices and removed non-LLVM directories and some GPL files.

Change-Id: If58e4a508b4de6780de67b72ab237180104c1b88

…x:aa6473684ac

Based on upstream llvm : b0c1900 [ARM,MVE] Add reversed isel patterns for MVE `vcmp qN,rN`

Local changes since b3cb789:
a62196f Manual merge master:b0c1900820c into amd-gfx:aa6473684ac
aa64736 Merged master:1587c7e86f1 into amd-gfx:c4fabe0ca62
c4fabe0 Manually merged master:32dfbd131da into amd-gfx:668f0b909c2
668f0b9 Merged master:1583158042a into amd-gfx:742c4b581f8
742c4b5 Merged master:e9bf7a60a03 into amd-gfx:06bb84fb51f
06bb84f Merged master:3d6b53980ce into amd-gfx:cf4b9356a59
cf4b935 Merged master:86f07e826f4 into amd-gfx:1b898c6c158
1b898c6 Merged master:f7499011ca2 into amd-gfx:5980e79c13d
5980e79 Merged master:a12f588ebb1 into amd-gfx:d3cebd9c93a
d3cebd9 Merged master:fd9fa9995cd into amd-gfx:35089c4c3b6
35089c4 Merged master:fed17867cd4 into amd-gfx:065f7d6ebe6
065f7d6 Merged master:9a1c243aa5d into amd-gfx:3cc5daff06c
3cc5daf Merged master:d384ad6b636 into amd-gfx:b1a4e621b5a
b1a4e62 Merged master:ef150e2ea51 into amd-gfx:dbed94f8efc
dbed94f Merged master:592dd459242 into amd-gfx:cbf5809133d
cbf5809 Merged master:7d0b1d77b3d into amd-gfx:a850655dec9
a850655 Merged master:eb8710cb93a into amd-gfx:c8e1ec406d7
c8e1ec4 Merged master:49fb4a96e0b into amd-gfx:1613c2ba305
1613c2b Merged master:fdf3d1766bb into amd-gfx:82c58d0dd35
82c58d0 Merged master:59d3fbc227c into amd-gfx:b1e28d1cf0a
b1e28d1 Merged master:51adeae1c90 into amd-gfx:f5179b4e8c1
f5179b4 Merged master:15bc4dc9a89 into amd-gfx:d401164f02a

Added AMD modification notices and removed non-LLVM directories and some GPL files.

Change-Id: I2488ebcc3395e6214a722845c8d2c575170cf80c

…bcaed72

Based on upstream llvm : a9bb669 [FileCollector] Ignore empty paths.

Local changes since 9894965:
a3f66b0 Merged master:a9bb669e59f into amd-gfx:7404bcaed72
7404bca Merged master:a21940eac14 into amd-gfx:776f23f3a1f
776f23f Merged master:82dc32e2d45 into amd-gfx:f8723175451
f872317 Merged master:c502bae5241 into amd-gfx:e40ee12b6f1
e40ee12 Merge "[AMDGPU] Make WQM aware of Waterfall intrinsics" into amd-gfx
4dfd372 [AMDGPU] Extra fixes for "Use SGPR_128 instead of SReg_128"
c086c04 Reinstate "AMDGPU: Use SGPR_128 instead of SReg_128 for vregs"

Added AMD modification notices and removed non-LLVM directories and some GPL files.

Change-Id: Ic9aa663cafa27a70255b545fadb1142d478c6d4f

…Waterfall intrinsics

Based on upstream llvm : 339502c [clangd] Reland b5135a8: Fix a crash in expected types

Local changes since cc9adb3:
5e3bf90 AMDGPU: Partially revert Make WQM aware of Waterfall intrinsics
3e8531d AMDGPU: Fix lit test checks with dag option
0da4840 Manual merge master:339502cc8ab into amd-gfx:a3f66b052d7

Added AMD modification notices and removed non-LLVM directories and some GPL files.

Change-Id: I1a02d9a144841e2bfe849c1ed97bea1dff663bd1

… to 0 or 1"

Based on upstream llvm : e9e1daf [ARM] Remove VHADD patterns

Local changes since 728902d:
cad4275 Revert "AMDGPU: Change boolean content type to 0 or 1"
e9043c4 Merged master:e9e1daf2b9e into amd-gfx:e99a753251e
e99a753 Merged master:3b0b7536a31 into amd-gfx:64b7877eaf8
64b7877 Merged master:19daa21f841 into amd-gfx:f034d7824a1
f034d78 Merged master:bc7f1df6b61 into amd-gfx:3295d541ef7
3295d54 Merged master:acd7fe8636a into amd-gfx:41e478fb64a
41e478f Merged master:f39277c1d37 into amd-gfx:448e14f2c88
448e14f Merged master:2e3c040ee06 into amd-gfx:6a77ef46e2d
6a77ef4 Merged master:943d8326dd3 into amd-gfx:0b6cee493f3
0b6cee4 Merged master:bb7d75ef1df into amd-gfx:23891d0bd4b
23891d0 Merged master:5e6b728763e into amd-gfx:f4c4257d522
f4c4257 Merged master:0f4383faa75 into amd-gfx:b06bbd87396
b06bbd8 Merged master:a29aa471062 into amd-gfx:52900510643
5290051 Merged master:3b35603a56b into amd-gfx:aca1eb387fa
aca1eb3 Merged master:d11dc9e77b6 into amd-gfx:d4d1cb7cfcf
d4d1cb7 Merged master:49a2b2a3d2c into amd-gfx:48b7fbb31f9
48b7fbb Merged master:d7be3eab5c0 into amd-gfx:1bdf52add2d
1bdf52a Merged master:8805316172a into amd-gfx:36c2fd72e78
36c2fd7 Merged master:5f8b8d28204 into amd-gfx:68f7718e978
68f7718 [AMDGPU] Extend the pre-gfx8 vccz bug workaround
d34946f Merge "AMDGPU: Update llvm.amdgcn.mfma.ll fix to match upstream version" into amd-gfx
e0f4c8d Merged master:7fbaa8097ec into amd-gfx:63502dc8564
63502dc Merged master:d1782133d96 into amd-gfx:17856c3f0bd
17856c3 Merged master:29b4d8f19e3 into amd-gfx:5b66d8d1fb7
5b66d8d Merged master:e841029aef7 into amd-gfx:fd06200fd90
fd06200 Merged master:bae5aac1ff4 into amd-gfx:bb5eee37b2f
bb5eee3 Merged master:01e8dd2e7a8 into amd-gfx:148e72f8974
148e72f Merged master:80cd6b6e043 into amd-gfx:28ca29a47cf
28ca29a Merged master:6b2431e0c2a into amd-gfx:fb843514f54
fb84351 Merged master:cb15ba84fe7 into amd-gfx:2c47006251b
2c47006 Merged master:96cf5c8d478 into amd-gfx:36a59782837
36a5978 Merged master:0b0dca9f6fe into amd-gfx:572453d9582
572453d Merged master:b9a26a80c81 into amd-gfx:64a41bc33bd
64a41bc Merged master:3b901ce3675 into amd-gfx:6d0babc8a6d
6d0babc Merged master:4dc2fb123dc into amd-gfx:f3580a1dc82
f3580a1 Merged master:1b9ef3bbb59 into amd-gfx:a8ee5c870a9
a8ee5c8 Merged master:d3fec7fb456 into amd-gfx:5e3bf90389a

Added AMD modification notices and removed non-LLVM directories and some GPL files.

Change-Id: Id8c12084797e2733736f4fb38e7f8283fdc5bef6

This reverts commit 31479d8.

Change-Id: I04bc9c209e06704bdc23e42e08af1634d91ae002

… to 0 or 1"

Based on upstream llvm : a9bb669 [FileCollector] Ignore empty paths.

Local changes since cc9adb3:
1532478 Revert "AMDGPU: Change boolean content type to 0 or 1"

Added AMD modification notices and removed non-LLVM directories and some GPL files.

Change-Id: Ie6a2f1013fea74b803d84bc8f8c367be74a74b8c

amd-gfx-legal-branch2 was created just to cherry-pick the fix
1532478 Revert "AMDGPU: Change boolean content type to 0 or 1"
for an already underway testing cycle.

That fix is already in amd-gfx-legal. Merging amd-gfx-legal-branch2
ensures we have an unbroken history when pushing out to GPUOpen drivers
on Github.

Change-Id: I75474b46b9c3679fa6024e0ff2b53ab568b3cbbf

… with undefs"

This reverts commit f575f12.

Change-Id: I7ff1354de1a7894c3f2c1f10b86b7c4ca3a0ca96

…le simplification for mask with undefs"

Based on upstream llvm : e9e1daf [ARM] Remove VHADD patterns

Local (non-upstream) changes since 9dad443:
198b0c7 Revert "[InstCombine] remove identity shuffle simplification for mask with undefs"

Added AMD modification notices and removed non-LLVM directories and some GPL files.

Change-Id: I9283b44ac9c307eebf010d41754dbdb28acc7520

…33143d1

Based on upstream llvm : 170ee64 [clang-tidy] Link shared library clangTidyOpenMPModule to library LLVMFrontendOpenMP

Local changes since cc0df5a:
9333d68 Merged master:170ee645f4d into amd-gfx:817733143d1
8177331 Merged master:6dad5e441db into amd-gfx:e29b386cb9a
e29b386 Merged master:d32484f40cb into amd-gfx:8980a783ffd
8980a78 Merged master:9ed681f9261 into amd-gfx:999cf270203
999cf27 Merged master:a38396939c5 into amd-gfx:763ce7cebd8
763ce7c Merged master:03a242bd41e into amd-gfx:b48a1ce2a82
b48a1ce Revert "[InstCombine] remove identity shuffle simplification for mask with undefs"
6ad9050 Merged master:2c63e8e36df into amd-gfx:f4c51959c4b
f4c5195 Merged master:39ccc099c90 into amd-gfx:9da89266d74
9da8926 Merged master:4dac97eb1e6 into amd-gfx:12c2f1bbf74
12c2f1b Merged master:a9f10ebffaa into amd-gfx:4765caf2752
4765caf Merged master:01e5290b49b into amd-gfx:d6d21f5cf6c
d6d21f5 Merged master:09311459e37 into amd-gfx:0f31e70c1aa
0f31e70 Merged master:41eeded8043 into amd-gfx:936fb7dd0a6
936fb7d Merged master:82f6ae5433c into amd-gfx:f07e6001b81
f07e600 Merged master:cd04e8349bd into amd-gfx:12ed18ff8c4
12ed18f Merged master:46db6068342 into amd-gfx:e5ca2af09e0
e5ca2af Merged master:c4c464f8a50 into amd-gfx:de0adae431b
de0adae Merged master:5595249e48e into amd-gfx:9ddf7c26de0
9ddf7c2 Merged master:8bf31e28d7b into amd-gfx:6a1ebdb306e
6a1ebdb Merged master:409350deeaf into amd-gfx:9b5c6e5fe65
9b5c6e5 Merged master:057626b4393 into amd-gfx:b253b7e85b8
b253b7e Merged master:33f93ea23a0 into amd-gfx:1758334b25d
1758334 Merged master:3ebfab70958 into amd-gfx:0be2e48798b
0be2e48 Merged master:dcf11c5e86c into amd-gfx:fab49ccd7ae
fab49cc Merged master:4f728bfc13c into amd-gfx:cad42751dee

Added AMD modification notices and removed non-LLVM directories and some GPL files.

Change-Id: I88a97fb3e54619c28d204de4eda0c8f9afff835b

…a4f3b3

Based on upstream llvm : fce1a6f Revert "AMDGPU: Try to commute sub of boolean ext"

Local changes since 0549a86:
131b828 Merge master:fce1a6f5848 into amd-gfx:9e2b7a4f3b3
9e2b7a4 Revert "Revert "AMDGPU: Change boolean content type to 0 or 1""
296f1a2 Merged master:7b774b7cd48 into amd-gfx:9333d68d986

Added AMD modification notices and removed non-LLVM directories and some GPL files.

Change-Id: I6fc27f14d2679f78e0e85a2b66e41f370f3d7651

…2be294b

Based on upstream llvm : 0f0330a [PowerPC] Legalize rounding nodes

Local changes since c22b899:
724d215 Merged master:0f0330a7870 into amd-gfx:4d562be294b
4d562be Merged master:948e745270d into amd-gfx:6760a4d8875
6760a4d Merged master:4a188fdfa79 into amd-gfx:e10a557109a
e10a557 Merged master:36ae255663c into amd-gfx:2b14c805739
2b14c80 Merged master:134ef0fb4b9 into amd-gfx:4d73740ec7e
4d73740 Merged master:3356e268f6c into amd-gfx:3d542200e83
3d54220 Merged master:e25e3d75850 into amd-gfx:8545c1fc925
8545c1f Merged master:cda94d3e8ae into amd-gfx:a78cf91cc1a
a78cf91 Merged master:e2d9f4e6a28 into amd-gfx:1291a95764f
1291a95 Merged master:e308a0ca15a into amd-gfx:8b31d4bb755
8b31d4b Merged master:54c52242034 into amd-gfx:669a5b9da2e
669a5b9 Merged master:d2a8e14177f into amd-gfx:25c967a1eec
25c967a Merged master:80c45e49c33 into amd-gfx:7522b40c1cb
7522b40 Merged master:1a2d2b492a3 into amd-gfx:8f52c0ef660
8f52c0e Merged master:8304781cae9 into amd-gfx:c64ea0409b2
c64ea04 Merged master:c7c05b0c8a0 into amd-gfx:f946f65516c
f946f65 Merged master:e40ac74dacd into amd-gfx:45c4cfde3cf
45c4cfd Merged master:982a9e3d46b into amd-gfx:f2ac07a81ed
f2ac07a Merged master:76d294cb874 into amd-gfx:0185fe179ea
0185fe1 Merged master:6d5e35e89d7 into amd-gfx:f9336878686
f933687 Merged master:ff92c56ef97 into amd-gfx:fca8d3e2414
fca8d3e Merged master:a9c845395f8 into amd-gfx:96f3f925d93
96f3f92 Merged master:e498be57387 into amd-gfx:b8f35abb804
b8f35ab Merged master:88a973cf688 into amd-gfx:a1a4da7d53a
a1a4da7 Merged master:40425183352 into amd-gfx:c99629390cb
c996293 Merged master:830e08b98bc into amd-gfx:4b00afd8032
4b00afd Manually Merged master:308b8b76cee into amd-gfx:4c172c4c298
4c172c4 Merged master:345f59667d8 into amd-gfx:c7c3b88d580
c7c3b88 Merged master:f8495017f02 into amd-gfx:a6cdb6608ab
a6cdb66 Revert "Revert "[InstCombine] remove identity shuffle simplification for mask with undefs""
8d1fae4 Merged master:959ed0e2944 into amd-gfx:131b8289ffd

Added AMD modification notices and removed non-LLVM directories and some GPL files.

Change-Id: I991443a941e8316f431a6074231217ba637d41b2

…-gfx:7c951d6eaf5

Based on upstream llvm : 6d6a459 [DWARF5][clang]: Added support for DebugInfo generation for auto return type for C++ member functions.

Local (non-upstream) changes since 08268e9:
821d322 Fix up tests to work with merge of master:a000f2e53f5
d366c9a Fix up tests to work with merge of master:1247865fe02

Added AMD modification notices and removed non-LLVM directories and some GPL files.

Change-Id: I12d8889fc67c73d71d62d8ffe836a084fe1d8de2

…-gfx:7c951d6eaf5

This is the first amd-gfx-legal that includes all llvm-project files,
not just llvm itself.

Based on upstream llvm : 6d6a459 [DWARF5][clang]: Added support for DebugInfo generation for auto return type for C++ member functions.

No local changes since 1ecf0a1.

Added AMD modification notices and removed some GPL files.

Change-Id: I43433157887114e29540eefb57daf2d4ea5de1d7

…-gfx:e9c2e262572

Based on upstream llvm : b54aa05 Update clang-interpreter example to incorporate changes in ce2207a.

Local changes since b8057d9:
7ebe085 Manually merged master:b54aa053d3a into amd-gfx:e9c2e262572
e9c2e26 Manually merged master:25afe91fd1b into amd-gfx:66dfcd6fd7a
66dfcd6 Manual merge master:cfd366ba74c into amd-gfx:293ea4504e7

Added AMD modification notices and removed some GPL files.

Change-Id: Id032693f00003a779b46bc6c6c49aafbcd845beb

…ills

Based on upstream llvm : b54aa05 Update clang-interpreter example to incorporate changes in ce2207a.

Local changes since 861404a:
0cd3f3e [AMDGPU] Don't remove short branches over kills

Added AMD modification notices and removed some GPL files.

Change-Id: I500f5772f5b844856a726845d2fbd4e84493fe80

…nstruction cater for non int values

Based on upstream llvm : 69558c8 [AArch64][SVE] Add remaining SVE2 intrinsics for uniform DSP operations

Local changes since 71e5ca0:
f54c614 AMDGPU: During img instruction ret value construction cater for non int values
366c47a Revert "AMDGPU/SILoadStoreOptimizer: Improve merging of out of order offsets"
f455871 Revert "[AMDGPU] Temporarily disabled immarg check in verifier"
fc8ae3c Test fixups for merge of master:69558c84871
d3e076a Manually merge master:69558c84871 into amd-gfx:0cd3f3ea2fb

Added AMD modification notices and removed some GPL files.

Change-Id: I226cb3f71a4bd48b8427b0206c65aa11fa6824b7